Cadence Digital and Custom/Analog Design Flows Certified by TSMC for Latest N3E and N4P Processes

Highlights:

• Companies collaborate to accelerate next-generation mobile, AI and hyperscale design innovation
• Customers actively designing with new N3E and N4P PDKs
• Cadence digital and custom/analog flows optimized to support N3E and N4P requirements, enabling optimal PPA results and improved designer productivity

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that its digital and custom/analog design flows have been certified for the TSMC N3E and N4P processes, supporting the latest Design Rule Manual (DRM). In addition, Cadence and TSMC delivered N3E and N4P process design kits (PDKs) and design flows to accelerate customer adoption and advance mobile, AI and hyperscale computing design innovation. Joint customers are actively designing with the new N3E and N4P PDKs, and several test chips have already been taped out, which demonstrates how Cadence solutions help customers improve engineering efficiency and maximize the power, performance and area (PPA) benefits offered by the latest TSMC process technologies.

The Cadence digital and custom/analog advanced-node solutions support the company’s Intelligent System Design^™ strategy, enabling system-on-chip (SoC) design excellence. To learn more about Cadence's advanced-node solutions, visit www.cadence.com/go/advndn3en4p.

N3E and N4P Digital Full-Flow Certification

Cadence worked closely with TSMC to ensure the digital full flow was optimized for TSMC’s advanced N3E and N4P process technologies. The complete RTL-to-GDS flow includes the Cadence Innovus^™ Implementation System, Quantus^™ Extraction Solution, Quantus Field Solver, Tempus^™ Timing Signoff Solution and ECO option, Pegasus^™ Verification System, Liberate^™ Characterization Solution and Voltus^™ IC Power Integrity Solution. Additionally, the Cadence Genus^™ Synthesis Solution and predictive iSpatial technology are enabled for the TSMC N3E and N4P process technologies.

The digital full flow offers several key capabilities that support the TSMC N3E and N4P process technologies, including the correlation between implementation and signoff results; enhanced via pillar support; efficient handling of large standard cell libraries containing many multi-height, voltage threshold (VT) and drive strength cells; low voltage cell characterization and certified signoff timing accuracy; and certified extraction accuracy with the Quantus Extraction Solution and Quantus Field Solver.

N3E and N4P Custom/Analog Flow Certification

The Cadence Virtuoso^® Design Platform, which includes the Virtuoso Schematic Editor, Virtuoso ADE Product Suite and Virtuoso Layout Suite EXL, the Spectre^® Simulation Platform, which includes Spectre X Simulator, Spectre Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS) and the Spectre RF Option, as well as the Virtuoso Application Library Environment and Voltus-Fi Custom Power Integrity Solution have achieved the latest TSMC N3E and N4P certifications. One unique capability that the Virtuoso Design Platform offers is tight integration with the Innovus Implementation System, which enhances the implementation methodology of mixed-signal designs using a common database. The Virtuoso Schematic Editor’s migration module in the Virtuoso Application Library Environment has been integrated and verified by TSMC.

The Virtuoso Schematic Editor, the Virtuoso ADE Suite and the integrated Spectre X Simulator have been optimized for the custom design reference flow (CDRF) for managing corner simulations, statistical analyses, design centering and circuit optimization. Furthermore, the CDRF’s Virtuoso Layout Suite EXL has been enhanced for efficient layout implementation, which provides customers with several features, including a unique row-based implementation methodology with interactive, assisted features for placement, routing, fill and dummy insertion; enhanced analog migration and layout reuse functionality; integrated parasitic extraction and EM-IR checks and integrated physical verification capabilities.

“Through our latest collaboration with Cadence, we’re making it easy for customers to benefit from the significant power and performance boosts of our latest N3E and N4P process technologies to drive design innovation forward,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “Our customers have to develop designs at an exceptionally rapid pace to keep up with market demands, and the design flows’ certification gives customers confidence that they can use our technologies to achieve design goals and get to market faster.”

“Our digital and custom/analog flows are packed with features that enable our customers to achieve optimal PPA while improving engineering productivity when creating N3E and N4P designs,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “By working closely with TSMC, we’re helping customers achieve SoC design excellence across a variety of market segments such as mobile, AI and hyperscale, and we’re looking forward to seeing many successful advanced-node innovations.”

About Cadence

Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

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Cadence announced that its digital and custom/analog design flows have been certified for the TSMC N3E and N4P processes, supporting the latest Design Rule Manual, accelerating mobile, AI and hyperscale computing design innovation.